Our Pi
Papers 1. “Dynamic Neural Controller as an E-diagnostic Tool,” Proceedings of the Asia AEC/APC Symposium IV, November 2006 (J. Card, A. Cao, W. Chan, W. Martin, C. Beal, G. Boone,A. Wong, and D. Kelly). 2. “Beta Test Results for a Yield Optimizer,” Proceedings of the AEC/APC Symposium XVIII, September 2006 (J. Card, A. Cao, W. Martin, P. Fearon, L. Krott, and A. Dries). 3. “Significant yield improvement for semiconductor production line using NeuMath Yield Optimizer,” GESTS International Transactions on Computer Science and Engineering, Vol. 29, No. 1, March 2006 (J. Card, A. Cao, W. Chan, W. Martin, P. Fearon, L. Krott, and A. Dries). 4. “A Neural Network-based Yield Optimizer for Semiconductor Manufacturing,” Proceedings of the AEC/APC Symposium XVII, September 2005 (J. Card, A. Cao, W. Chan, W. Martin, C. Cuneo, and J. Hyde). 5. “Beta Test Results for a Yield Optimizer,” Proceedings of the ISMI, September 2006 (J. Card, A.Cao, W. Martin, P. Fearon, L. Krott, and A. Dries). 6. “The Use of Unified APC/FDC in the Control of a Metal Etch Area,” Proceedings, 15th IEEE/SEMI ASMC, May 2004 (J Card, J. Hyde, W. Chan, and A. Cao). 7. “Impacts of Maintenance Input on the Prediction Accuracy of an APC Controller,” Proceedings of the ASMC, May 2003 (A. Cao, J Card, and W. Chan). 8. “Using Maintenance Input Data to Increase the Prediction Accuracy of APC Strategies,” MicroMagazine, June 2003 (A. Cao, J. Card and W. Chan). 9. “Impacts of Maintenance Input on the Prediction Accuracy of an APC Controller,” Micro Magazine, March 2003(J. Card, A. Cao, and W. Chan). 10. “Using Neural Networks for Intelligent Plasma Etch Process Control,” Solid State Technology, pp. 33–36, November 2002 (J. Card, L. Laurin). 11. “A Study in Dynamic Neural Control of Semiconductor Fabrication Processes,” IEEE Transactions on Semiconductor Manufacturing, Vol. 13, No. 3, pp. 359–365, August 2000. “Run-to-run Process Control of a Plasma Etch Process with Neural Network Modeling,” Quality and Reliability Engineering International, Vol. 14, No. 4, pp. 247–260, 1998 (J. Card, M. Naimo and W. Ziminsky). 13. “Neural Network Optimization Routines for Plasma Etch Process Control and Efficient Parts replacement,” Proceedings of the 2nd International Symposium on Process Control,Diagnostics, and Modeling in Semiconductor Manufacturing, pp. 28–37, November 1997 (D.L. Sniderman, J. Card and C. Klimasauskas). 14. Plasma Etch Process Control with a Neural Network-based Prediction Model,” Proceedings of the 2nd International Symposium on Process Control, Diagnostics, and Modeling in Semiconductor Manufacturing, pp. 19–27, November 1997 (J. Card, D.L. Sniderman and C. Klimasauskas). 15. “Dynamic Neural Control for Plasma Etch Process,” IEEE Transactions on Neural Networks. Vol. 8, No.4, pp. 883–901, May 1997 (J. Card, D. L. Sniderman and C. Klimasauskas). 16. “Modeling Outcome of Mechanical Intervention after Cardiac Surgery,” Proceedings of the 1995 World Congress on Neural Networks, Vol. II, July 1995 (J. Card and P.I. Singh). 17. “Discrimination of Surface Textures Using Fractal Methods,” Material Research Society Symposium Proceedings, Vol. 367, pp. 113–118, 1995 (J. Card, J.M. Hyde and T. Giversen). 18. “SRAM Bitmap Shape Recognition and Sorting using Neural Networks,” IEEE Transactions on Semiconductor Manufacturing, Vol. 8, No. 3, pp. 326–332, 1995 (R.S. Collica. J. Card, and W. Martin). 19. “Target Factor and Neural Network Analyses Applied to Titanium Nitride Composition Recognition by AES,” Surface and Interface Analysis. Vol. 23, pp. 495–505, July 1995 (A.L. Testoni, J. Card, and L.A. LeTarte). 20. “Neural Network Approach to Automated Wirebond Defect Classification,” Proceedings of the ANNIE ’94, November 1994 (J. Card, A. McGowan and C. Reed). 1. “Intelligent Modeling of Process and Tool Health,” U.S. Patent No. 7020569, September 2003 (with A. Cao and W. Chan). “Intelligent Control for Process Optimization and Parts Maintenance,” U.S. Patent No. 6970857, September 2002 (J. Card, W. Chan and A. Cao). 2. “Advance Failure Prediction,” U.S. Patent No. 6915173, August 2002 (J. Card, W. Chan and E.A Rietman). 3. “Large Scale Process Control by Driving Factor Identification,” U.S. Patent No. 6904328, September 2001 (E.A. Rietman, J. Card). 4. “Scalable, Hierarchical Control for Complex Processes,” U.S. Patent No. 6810291, September 2001, (J. Card, E.A. Rietman). 5. “Systems and Method for Lights-out Manufacturing,” U.S. Patent Application No. 20060036345, August 2004 (J. Card, W. Chan and A. Cao). 6. “Filter Models for Dynamic Control of Complex Processes,” U.S. Patent Application No. 20040039556, August 2003 (J. Card, W. Chan and A. Cao). 7. “Control of Complex Manufacturing Processes Using Continuous Process Data,” U.S. Patent Application No. 20040019470, July 2002 (with W. Chan and A. Cao).
Presentations and Published Abstracts
1. "Dynamic Neural Controller as an E-diagnostic Tool," Proceedings of the Asia AEC/APC Symposium IV, November 2006 (J. Card, A. Cao, W. Chan, W. Martin, C. Beal, G. Boone, A. Wong, and D. Kelly). 2. “Beta Test Results for a Yield Optimizer,” Proceedings of the AEC/APC Symposium XVIII, September 2006 (J. Card, A. Cao, W. Martin, P. Fearon, L. Krott, and A. Dries). 3. “A Neural Network-based Yield Optimizer for Semiconductor Manufacturing,” Proceedings of the AEC/APC Symposium XVII, September 2005 (J. Card, A. Cao, W. Chan, W. Martin, C. Cuneo, and J. Hyde). 4. “Scalable Hierarchical Yield Control System for Semiconductor Manufacturing: A Feasibility Study,” Proceedings of the AEC/APC Symposium Asia, 2004 (with B. Martin, W. Chan, J. Hyde, Y. Lai, P. Fearon, and J. Doxsey). 5. “Relationship Between in-situ Information and ex-situ Metrology in Metal Etch Processes,” Proceedings of the AEC/APC Symposium Asia, 2004 (J. Card, A. Cao, W. Chan, W. Martin, and Y. Lai). 6. “Target-oriented Operations of 300mm wafer production lines - necessities and hurdles of advanced process controls,” Proceedings of the ICRA, September 2003 (J. Card). 7. “Dynamic Update Scheme for Real-Time Adaptive Process Modeling,” Proceedings of the AEC/APC Symposium XV, September 2003 (J. Card, A. Cao, W. Chan, W. Martin, and J Hyde). 8. “Advanced Analysis of Dynamic Neural Control Advisories for Process Optimization and Parts Maintenance,” Proceedings of the AEC/APC Symposium XIV, September 2002 (J. Card, W. Chan, W. Martin, and J. Morgan). 9. “Dynamic Neural Controller: Test Results for LAM Plasma Etch Applications,” Proceedings of the XII SEMATECH AEC/APC Symposium, September 2001 (J. Card, W. Chan, M. Ellis, W. Martin, E. Rietman, and P. Walker). 10. “Optimizing a Plasma Etch Process with a Neural Network-Based Model Predictive Controller”, Proceedings of the VIII SEMATECH AEC/APC Workshop, September 1996 (J. Card).
